1. Cross-References to Related Applications
This application relies for priority upon Korean Patent Application No. 2001-3426, filed on Jan. 20, 2001, the contents of which are herein incorporated by reference in their entirety.
2. Field of the Invention
The present invention generally relates to a NAND-type flash memory device and a method of forming the same. More specifically, the invention is directed to a NAND-type flash memory device having only minimal leakage current resulting from a short channel effect within a string selection transistor and a ground selection transistor, and a method of forming the same.
3. Description of the Prior Art
As semiconductor devices become more highly integrated due to improved semiconductor manufacturing techniques, the channel lengths within transistor devices are necessarily reduced. One unfortunate byproduct of reduced structure size is punchthrough, where the depletion regions of a source and a drain merge together and thereby prevent the channel current from being easily controlled. One known prior art method of preventing punchthrough is to increase the impurity concentration within the substrate. This impurity doping enables the depletion regions to be narrow such that they do not merge together.
Unfortunately, raising the impurity concentration of a channel or a source/drain region increases the intensity of the electric field formed at the junction area between the regions. Thus, raising the impurity concentration using methods known in the prior art causes additional problems of hot carriers or a corresponding increase in the leakage current from high conductive regions to the substrate.
Since a NAND-type flash memory device is a highly integrated semiconductor device, it also suffers from the punchthrough as described above. FIG. 1 is a top plan view showing a string portion of the device comprising a formation unit in a cell area of a conventional NAND-type flash memory. A plurality of cell memory transistors are serially connected to each other, as by wordline WL which crosses over each active region. In each string, there are a string selection transistor and a bitline contact BC at one end of the cell memory transistors, and there are a ground selection transistor and a common source line CSL at the other end. The string selection transistor is formed at a position where a string select line SSL crosses over an active region, while the ground selection transistor is formed at a position where a ground select line GSL crosses over an active region.
The string select line SSL and the ground select line GSL are continuously coupled along a line, on which a floating gate layer is not floated. The floating gate layer (shown in FIG. 4 at 13) is patterned at a wordline WL where a memory cell array is formed, isolating and floating SSL and GSL in each transistor.
FIG. 2 is a cross-sectional view taken along line Ixe2x80x94I of FIG. 1. As the integration level of flash memory devices increases, both the wordline-to-wordline space xe2x80x9caxe2x80x9d and the channel length decrease while the wordline height xe2x80x9cbxe2x80x9d increases relative to the length of the device structuresxe2x80x94in other words, the aspect ratio increases. The areas where bitline contact BC and common source line CSL are formed, denoted by the dimensions xe2x80x9ccxe2x80x9d and xe2x80x9cdxe2x80x9d, are wider than the space xe2x80x9caxe2x80x9d. In this case, the region xe2x80x9ccxe2x80x9d spans the distance from a string select line SSL1 of one string to a string select line SSL0 of an adjacent opposite string, and the region xe2x80x9cdxe2x80x9d spans the distance from a ground select line GSL1 of one string to a string select line GSL2 of an adjacent opposite string.
With highly integrated NAND-type flash memory devices, punchthrough tends to occur in the string selection transistor and the ground selection transistor. Furthermore, increased integration using known methods creates a greater likelihood of leakage current caused by short channel effects. One method for addressing these limitations in NAND-type flash memory devices is to use ion implantation to form a heavily doped impurity layer P over a surface of a semiconductor substrate when a well Pxe2x88x92 for preventing punchthrough is formed on the substrate, as shown in FIG. 3.
Further prior art process steps are illustrated in FIG. 4 where the device includes a gate insulating layer 11, a floating gate layer 13, a dielectric layer 15, and a control gate layer 17 sequentially formed on a substrate 10. These material layers are patterned respectively or together, forming a gate line that conceptually includes a wordline, a string select line, and a ground select line. Impurities are then implanted into those portions of the substrate exposed by patterning a gate line, the impurities thereby forming a source/drain region 19. In this 30 case, the type of impurities used is contrary to that of the well. However, such a structure shown in FIG. 4 exhibits increased junction leakage current in the cell memory transistor, and thereby creates errors in programming the cell memory (Choi, et al., xe2x80x9cA 0.15 xcexcm NAND flash memory with 0.11 xcexcm2 cell size for 1 Gbit flash memory,xe2x80x9d IEDM 2000, accepted: Suh, et al., xe2x80x9cA 3.3V 32 Mb flash memory with incremental step pulse programming scheme,xe2x80x9d IEEE. J. Solid-state Circuit, Vol. 30, No. 11, pp. 1149-1156, November 1995.).
Accordingly, it is desired to develop a method for maintaining the ion concentration level in a cell memory transistor at a particular level without performing an ion implantation for preventing a punchthrough, and to suppress a leakage current resulting from a short channel effects in a string selection transistor or a ground selection transistor.
It is an object of the present invention to provide a NAND-type flash memory device that is able to prevent memory dysfunction caused by punchthrough at a drain region of a string selection transistor and a merge area in which a source region of a ground selection transistor merges with their channel in each string of the NAND-type flash memory device, and a method of forming the same.
It is another object of the present invention to provide a NAND-type flash memory device that is able to prevent an increase in a junction leakage current and resulting programming disturbance phenomenon when a heavily doped pocket for preventing punchthrough is installed in a cell memory transistor of the NAND-type flash memory device, and a method of forming the same.
One method suggested in the literature for addressing these objects includes forming heavily doped pocket areas in the device during processing. (Hori, xe2x80x9cA 0.1 xcexcm CMOS technology with Tilt-Implanted Punchthrough Stopper,xe2x80x9d IEDM 1994, pp. 75-78: xe2x80x9cField effect-transistor with asymmetrical structure,xe2x80x9d U.S. patent 1986, Codella, et al.). Nonetheless, the method for forming such pockets is nontrivial and has proven very difficult for highly integrated devices such as NAND-type flash memories. The present invention addresses this deficiency.
A NAND-type flash memory device conventionally includes a string selection transistor, a plurality of cell memory transistors, a ground selection transistor that are serially connected; a bitline contact that is connected to a drain region of the string selection transistor; and a common source line that is connected to a source area of the ground selection transistor. According to one feature of the present invention, heavily doped pockets for preventing punchthrough are formed in the NAND-type flash memory. Impurities are doped definitely to one interface between a channel and a drain region of the string selection transistor, and to another interface between a channel and a source region of the ground selection transistor.
The pockets, which are highly doped areas, can penetrate into an adjacent channel region with a constant distance. Preferably, the pockets control an ion implantation energy, enabling a maximum concentration point to reach the same level as the depth of a source/drain-substrate junction area or a source/drain-well junction area. Usually, the heavily doped impurities are identical in type to impurities that are doped to a channel.
According to another feature of the invention, a gate electrode profile is formed on a plurality of active regions that are parallel with each other. In the profile, a gate insulating layer, a floating gate layer, a dielectric layer, and a control gate layer are sequentially stacked. The gate electrode profile is patterned to form gate lines that are vertical to the active region. In the gate lines, a string select line, a plurality of wordlines, and a ground select line are sequentially formed to compose a construction unit (generally called xe2x80x9cstringxe2x80x9d) of a NAND-type flash memory, thereby forming a string selection transistor, a cell memory transistor, and a ground selection transistor at a region across the active region. Using the gate lines as ion implantation masks, a tilted ion implantation is then carried out.
The angle of implantation is carefully controlled to carry out the ion implantation only to an active region adjacent to an opposite sidewall of the wordline out of both sidewalls of the string select line, and to an active region adjacent to an opposite sidewall of the wordline out of both sidewalls of the ground select line. In this case, an interlayer insulating layer, a bitline contact, a common source line, and a structure thereon are not formed yet. Since a conventional cell memory transistor is an N-channel transistor, the tilted ion implantation is carried out with P-type impurity ions.